View HLX6256_5326503.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

other ? read/write cycle times 17 ns (typical) 25 ns (-55 to 125 c) ? typical operating power <10 mw/mhz ? asynchronous operation ? jedec standard low voltage cmos compatible i/o ? single 3.3 v 0.3v power supply ? packaging options - 28-lead flat pack (0.500 in. x 0.720 in.) - 28-lead dip, mil-std-1835, cdip2-t28 - 36-lead flat pack (0.630 in. x 0.650 in.) - various multi-chip module (mcm) configurations 32k x 8 static ram?low power soi HLX6256 military & space products radiation ? fabricated with ricmos ? iv silicon on insulator (soi) 0.55 m low power process ? total dose hardness through 1x10 6 rad(sio 2 ) ? neutron hardness through 1x10 14 cm -2 ? dynamic and static transient upset hardness through 1x10 9 rad(si)/s ? dose rate survivability through 1x10 11 rad(si)/s ? soft error rate of <1x10 -10 upsets/bit-day ? latchup free general description the 32k x 8 radiation hardened static ram is a high performance 32,768 word x 8-bit static random access memory with industry-standard functionality. it is fabri- cated with honeywell?s radiation hardened technology, and is designed for use in low voltage systems operating in radiation environments. the ram operates over the full military temperature range and requires only a single 3.3 v 0.3v power supply. the ram is compatible with jedec standard low voltage cmos i/o. power consumption is typically less than 10 mw/mhz in operation, and less than 2 mw when de-selected. the ram read operation is fully asynchronous, with an associated typical access time of 14 ns at 3.3 v. honeywell?s enhanced soi ricmos ? iv (radiation insen- sitive cmos) technology is radiation hardened through the use of advanced and proprietary design, layout and pro- cess hardening techniques. the ricmos ? iv low power process is a simox cmos technology with a 150 ? gate oxide and a minimum drawn feature size of 0.7 m (0.55 m effective gate length?l eff ). additional features include tungsten via plugs, honeywell?s proprietary sharp pla- narization process and a lightly doped drain (ldd) struc- ture for improved short channel reliability. a 7 transistor (7t) memory cell is used for superior single event upset hardening, while three layer metal power bussing and the low collection volume simox substrate provide improved dose rate hardening. features
HLX6256 2 *not available in 28-lead dip or 28-lead flat pack signal definitions a: 0-14 address input pins which select a particular eight-bit word within the memory array. dq: 0-7 bidirectional data pins which serve as data outputs during a read operation and as data inputs during a write operation. ncs negative chip select, when at a low level allows normal read or write operation. when at a high level ncs forces the sram to a precharge condition, holds the data output drivers in a high impedance state and disables all input buffers except ce. if this signal is not used it must be connected to vss. nwe negative write enable, when at a low level activates a write operation and holds the data output drivers in a high impedance state. when at a high level nwe allows normal read operation. noe negative output enable, when at a high level holds the data output drivers in a high impedance state. when at a low level, the data output driver state is defined by ncs, nwe and ce. if this signal is not used it must be connected to vss. ce* chip enable, when at a high level allows normal operation. when at a low level ce forces the sram to a precharge condition, holds the data output drivers in a high impedance state and disables all the input buffers except the ncs input buffer. if this signal is not used it must be connected to vdd. ncs ce* nwe noe mode dq l h h l read data out l h l x write data in h x xx xx deselected high z x l xx xx disabled high z truth table functional diagram notes: x: vi=vih or vil xx: vss vi vdd noe=h: high z output state maintained for ncs=x, ce=x, nwe=x ncs a:0-8,12-13 ce nwe noe we ? cs ? ce nwe ? cs ? ce ? oe column decoder data input/output row decoder 32,768 x 8 memory array a:9-11, 14 # signal all controls must be enabled for a signal to pass. (#: number of buffers, default = 1) 1 = enabled signal 4 dq:0-7 (0 = high z) ? ? ? ? ? ? 8 8 11
3 HLX6256 total dose 1x10 6 rad(sio 2 ) transient dose rate upset (3) 1x10 9 rad(si)/s transient dose rate survivability (3) 1x10 11 rad(si)/s soft error rate (ser) <1x10 -10 upsets/bit-day neutron fluence 1x10 14 n/cm 2 parameter limits (2) test conditions radiation hardness ratings (1) units t a =25 c total ionizing radiation dose the sram will meet all stated functional and electrical specifications over the entire operating temperature range after the specified total ionizing radiation dose. all electrical and timing performance parameters will remain within specifications after rebound at vdd = 3.6 v and t =125 c extrapolated to ten years of operation. total dose hardness is assured by wafer level testing of process monitor transis- tors and ram product using 10 kev x-ray and co60 radiation sources. transistor gate threshold shift correla- tions have been made between 10 kev x-rays applied at a dose rate of 1x10 5 rad(sio 2 )/min at t = 25 c and gamma rays (cobalt 60 source) to ensure that wafer level x-ray testing is consistent with standard military radiation test environments. transient pulse ionizing radiation the sram is capable of writing, reading, and retaining stored data during and after exposure to a transient ionizing radiation pulse up to the transient dose rate upset specification, when applied under recommended operat- ing conditions. to ensure validity of all specified perfor- mance parameters before, during, and after radiation (timing degradation during transient pulse radiation (tim- ing degradation during transient pulse radiation is 10%), it is suggested that stiffening capacitance be placed on or near the package vdd and vss, with a maximum induc- tance between the package (chip) and stiffening capaci- tance of 0.7 nh per part. if there are no operate-through or valid stored data requirements, typical circuit board mounted de-coupling capacitors are recommended. (1) device will not latch up due to any of the specified radiation exposure conditions. (2) operating conditions (unless otherwise specified): vdd=3.0 v to 3.6 v, ta=-55 c to 125 c. (3) not guaranteed with 28?lead dip. 1 mev equivalent energy, unbiased, t a =25 c t a =125 c, adams 10% worst case environment pulse width 50 ns, x-ray, vdd=4.0 v, t a =25 c pulse width 1 s the sram will meet any functional or electrical specifica- tion after exposure to a radiation pulse of up to the transient dose rate survivability specification, when applied under recommended operating conditions. note that the current conducted during the pulse by the ram inputs, outputs and power supply may significantly exceed the normal operat- ing levels. the application design must accommodate these effects. neutron radiation the sram will meet any functional or timing specification after exposure to the specified neutron fluence under recommended operating or storage conditions. this as- sumes an equivalent neutron energy of 1 mev. soft error rate the sram is immune to single event upsets (seu?s) to the specified soft error rate (ser), under recommended oper- ating conditions. this hardness level is defined by the adams 10% worst case cosmic ray environment for geo- synchronous orbits. latchup the sram will not latch up due to any of the above radiation exposure conditions when applied under recom- mended operating conditions. fabrication with the simox substrate material provides oxide isolation between adja- cent pmos and nmos transistors and eliminates any potential scr latchup structures. sufficient transistor body tie connections to the p- and n-channel substrates are made to ensure no source/drain snapback occurs. radiation characteristics
HLX6256 4 vdd positive supply voltage (2) -0.5 6.5 v vpin voltage on any pin (2) -0.5 vdd+0.5 v tstore storage temperature (zero bias) -65 150 c tsolder soldering temperature ? time 270?5 c?s pd total package power dissipation (3) 2.0 w iout dc or average output current 2.0 ma vprot esd input protection voltage (4) 2000 v 28 fp/36 fp 2 28 dip 10 tj junction temperature 175 c parameter symbol parameter max symbol test conditions worst case units capacitance (1) symbol test conditions min max typical (1) units vdr data retention voltage 1.65 v idr data retention current 300 a jc thermal resistance (jct-to-case) (1) this parameter is tested during initial design characterization only. recommended operating conditions symbol max typ description parameter min worst case (2) c/w units vdd supply voltage (referenced to vss) 3.0 3.3 3.6 v ta ambient temperature -55 25 125 c vpin voltage on any pin (referenced to vss) -0.3 vdd+0.3 v min typical (1) ci input capacitance 7 pf vi=vdd or vss, f=1 mhz co output capacitance 9 pf vio=vdd or vss, f=1 mhz units rating min max (1) typical operating conditions: ta= 25 c, pre-radiation. (2) worst case operating conditions: ta= -55 c to +125 c, post total dose at 25 c. data retention characteristics parameter (1) stresses in excess of those listed above may result in permanent damage. these are stress ratings only, and operation at the se levels is not implied. frequent or extended exposure to absolute maximum conditions may affect device reliability. (2) voltage referenced to vss. (3) ram power dissipation (iddsb + iddop) plus ram output driver power dissipation due to external loading must not exceed this specification. (4) class 2 electrostatic discharge (esd) input protection. tested per mil-std-883, method 3015 by desc certified lab. absolute maximum ratings (1) ncs=vdd=vdr vi=vdr or vss ncs=vdr vi=vdr or vss
5 HLX6256 iddsb1 static supply current 1.0 ma iddsbmf standby supply current - deselected 1.0 ma iddopw dynamic supply current, selected (write) 3.0 ma iddopr dynamic supply current, selected (read) 3.0 ma ii input leakage current -1 +1 a ioz output leakage current -1 +1 a vil low-level input voltage vih high-level input voltage dc electrical characteristics units test conditions min max worst case (2) symbol parameter typical (1) ncs=vdd, io=0, f=40 mhz vih=vdd io=0 vil=vss inputs stable f=1 mhz, io=0, ce=vih=vdd ncs=vil=vss f=1 mhz, io=0, ce=vih=vdd ncs=vil=vss vss vi vdd vss vio vdd output=high z 0.7xv dd v dd +.3 v march pattern v vdd = 3.6v 0.4 v vdd = 3.0v, iol = 8 ma 2.7 v vdd = 3.0v, ioh = -4 ma -0.3 0.3xv dd v march pattern v vdd = 3.0v vol low-level output voltage voh high-level output voltage (1) typical operating conditions: vdd=3.3 v, ta=25 c, pre-radiation. (2) worst case operating conditions: vdd=3.0 v to 3.6 v, ta=-55 c to +125 c, post total dose at 25 c. (3) all inputs switching. dc average current. dut output valid low output vref1 c l > 50 pf* 249 ? tester equivalent load circuit 2.2 v valid high output vref2 - + - + *c l = 5 pf for twlqz, tshqz, telqz, and tghqz
HLX6256 6 high impedance ncs noe data valid ce t avavr t avqv t axqx t slqv t slqx t shqz t ehqx t ehqv t glqx t glqv t ghqz t elqz address (nwe = high) data out tavavr address read cycle time 25 ns tavqv address access time 25 ns taxqx address change to output invalid time 3 ns tslqv chip select access time 25 ns tslqx chip select output enable time 5 ns tshqz chip select output disable time 14 ns tehqv chip enable access time (4) 25 ns tehqx chip enable output enable time (4) 5 ns telqz chip enable output disable time (4) 14 ns tglqv output enable access time 9 ns tglqx output enable output enable time 0 ns tghqz output enable output disable time 12.6 ns read cycle ac timing characteristics (1) worst case (3) symbol parameter typical -55 to 125 c units (2) min max (1) test conditions: input switching levels,vil/vih=0v/3v, input rise and fall times <1 ns/v, input and output timing reference levels shown in the tester ac timing characteristics table, capacitive output loading c l >50 pf, or equivalent capacitive output loading c l =5 pf for tshqz, telqz tghqz. for c l >50 pf, derate access times by 0.02 ns/pf (typical). (2) typical operating conditions: vdd=3.3 v, ta=25 c, pre-radiation. (3) worst case operating conditions: vdd=3.0 v to 3.6 v, post total dose at 25 c. (4) chip enable (ce) pin not available on 28-lead fp or dip.
7 HLX6256 address high impedance data out nwe data in data valid t avavw ncs ce t avwh t wlwh t avwl t wlqz t dvwh t whqx t whdx t slwh t ehwh t whax t whwl write cycle ac timing characteristics (1) symbol parameter typical -55 to 125 c units (2) min max worst case (3) tavavw write cycle time (4) 25 ns twlwh write enable write pulse width 20 ns tslwh chip select to end of write time 20 ns tdvwh data valid to end of write time 15 ns tavwh address valid to end of write time 20 ns twhdx data hold time after end of write time 0 ns tavwl address valid setup to start of write time 0 ns twhax address valid hold after end of write time 0 ns twlqz write enable to output disable time 12.6 ns twhqx write disable to output enable time 5 ns twhwl write disable to write enable pulse width (5) 5 ns tehwh chip enable to end of write time (6) 20 ns (1) test conditions: input switching levels, vil/vih=0v/3v, input rise and fall times <1 ns/v, input and output timing reference levels shown in the tester ac timing characteristics table, capacitive output loading >50 pf, or equivalent capacitive load of 5 pf for twlqz. (2) typical operating conditions: vdd=3.3 v, ta=25 c, pre-radiation. (3) worst case operating conditions: vdd=3.0 v to 3.6 v, -55 to 125 c, post total dose at 25 c. (4) tavavw = twlwh + twhwl (5) guaranteed but not tested. (6) chip enable (ce) pin not available on 28-lead fp or dip.
HLX6256 8 dynamic electrical characteristics read cycle the ram is asynchronous in operation, allowing the read cycle to be controlled by address, chip select (ncs), or chip enable (ce) (refer to read cycle timing diagram). to perform a valid read operation, both chip select and output enable (noe) must be low and chip enable and write enable (nwe) must be high. the output drivers can be controlled independently by the noe signal. consecutive read cycles can be executed with ncs held continuously low, and with ce held continuously high, and toggling the addresses. for an address activated read cycle, ncs and ce must be valid prior to or coincident with the activating address edge transition(s). any amount of toggling or skew between ad- dress edge transitions is permissible; however, data outputs will become valid tavqv time following the latest occurring address edge transition. the minimum address activated read cycle time is tavav. when the ram is operated at the minimum address activated read cycle time, the data outputs will remain valid on the ram i/o until taxqx time following the next sequential address transition. to control a read cycle with ncs, all addresses and ce must be valid prior to or coincident with the enabling ncs edge transition. address or ce edge transitions can occur later than the specified setup times to ncs; however, the valid data access time will be delayed. any address edge transition, which occurs during the time when ncs is low, will initiate a new read access, and data outputs will not become valid until tavqv time following the address edge transition. data outputs will enter a high impedance state tshqz time following a disabling ncs edge transition. to control a read cycle with ce, all addresses and ncs must be valid prior to or coincident with the enabling ce edge transition. address or ncs edge transitions can occur later than the specified setup times to ce; however, the valid data access time will be delayed. any address edge transition which occurs during the time when ce is high will initiate a new read access, and data outputs will not become valid until tavqv time following the address edge transition. data outputs will enter a high impedance state telqz time following a disabling ce edge transition. write cycle the write operation is synchronous with respect to the address bits, and control is governed by write enable (nwe), chip select (ncs), or chip enable (ce) edge transitions (refer to write cycle timing diagrams). to per- form a write operation, both nwe and ncs must be low, and ce must be high. consecutive write cycles can be performed with nwe or ncs held continuously low, or ce held continuously high. at least one of the control signals must transition to the opposite state between consecutive write operations. the write mode can be controlled via three different control signals: nwe, ncs, and ce. all three modes of control are similar, except the ncs and ce controlled modes actually disable the ram during the write recovery pulse. both ce and ncs fully disable the ram decode logic and input buffers for power savings. only the nwe controlled mode is shown in the table and diagram on the previous page for simplicity; however, each mode of control provides the same write cycle timing characteristics. thus, some of the parameter names referenced below are not shown in the write cycle table or diagram, but indicate which control pin is in control as it switches high or low. to write data into the ram, nwe and ncs must be held low and ce must be held high for at least twlwh/tslsh/ tehel time. any amount of edge skew between the signals can be tolerated, and any one of the control signals can initiate or terminate the write operation. for consecu- tive write operations, write pulses must be separated by the minimum specified twhwl/tshsl/teleh time. address inputs must be valid at least tavwl/tavsl/taveh time before the enabling nwe/ncs/ce edge transition, and must remain valid during the entire write time. a valid data overlap of write pulse width time of tdvwh/tdvsh/tdvel, and an address valid to end of write time of tavwh/ tavsh/tavel also must be provided for during the write operation. hold times for address inputs and data inputs with respect to the disabling nwe/ncs/ce edge transition must be a minimum of twhax/tshax/telax time and twhdx/tshdx/teldx time, respectively. the minimum write cycle time is tavav.
9 HLX6256 tester ac timing characteristics ing the need to create detailed specifications and offer benefits of improved quality and cost savings through standardization. reliability honeywell understands the stringent reliability require- ments for space and defense systems and has extensive experience in reliability testing on programs of this nature. this experience is derived from comprehensive testing of vlsi processes. reliability attributes of the ricmos tm process were characterized by testing specially designed irradiated and non-irradiated test structures from which specific failure mechanisms were evaluated. these specific mechanisms included, but were not limited to, hot carriers, electromigration and time dependent dielectric breakdown. this data was then used to make changes to the design models and process to ensure more reliable products. in addition, the reliability of the ricmos tm process and product in a military environment was monitored by testing irradiated and non-irradiated circuits in accelerated dy- namic life test conditions. packages are qualified for prod- uct use after undergoing groups b & d testing as outlined in mil-std-883, tm 5005, class s. the product is quali- fied by following a screening and testing flow to meet the customer?s requirements. quality conformance testing is performed as an option on all production lots to ensure the ongoing reliability of the product. quality and radiation hardness assurance honeywell maintains a high level of product integrity through process control, utilizing statistical process control, a com- plete ?total quality assurance system,? a computer data base process performance tracking system and a radia- tion-hardness assurance strategy. the radiation hardness assurance strategy starts with a technology that is resistant to the effects of radiation. radiation hardness is assured on every wafer by irradiating test structures as well as sram product, and then monitor- ing key parameters which are sensitive to ionizing radia- tion. conventional mil-std-883 tm 5005 group e testing, which includes total dose exposure with cobalt 60, may also be performed as required. this total quality approach ensures our customers of a reliable product by engineering in reliability, starting with process development and con- tinuing through product qualification and screening. screening levels honeywell offers several levels of device screening to meet your system needs. ?engineering devices? are available with limited performance and screening for breadboarding and/or evaluation testing. hi-rel level b and s devices undergo additional screening per the requirements of mil- std-883. as a qml supplier, honeywell also offers qml class q and v devices per mil-prf-38535 and are avail- able per the applicable standard microcircuit drawing (smd). qml devices offer ease of procurement by eliminat- 3 v 0 v vdd/2 vdd/2 0.4 v high z 2.7 v 1.7 v high z input levels* output sense levels high z = 2.2v * input rise and fall times <1 ns/v vdd-0.4v
HLX6256 10 e 1 e b d (width) (pitch) l top view u w x y capacitor pads f [1] bsc ? basic lead spacing between centers [2] where lead is brazed to package [3] parts delivered with leads unformed [4] lid connected to vss a b c d e e e2 e3 f g l q s u w x y 0.105 0.015 0.017 0.002 0.003 to 0.006 0.720 0.008 0.050 0.005 [1] 0.500 0.007 0.380 0.008 0.060 ref 0.650 0.005 [2] 0.035 0.004 0.295 min [3] 0.026 to 0.045 0.045 0.010 0.130 ref 0.050 ref 0.075 ref 0.010 ref all dimensions in inches 1 a lead alloy 42 [3] ceramic body c e2 g q kovar lid [4] e3 bottom view s index the 32k x 8 sram is offered in a custom 36-lead flat pack (fp), 28-lead fp, or standard 28-lead dip. each package is constructed of multilayer ceramic (al 2 o 3 ) and features internal power and ground planes. the 36-lead fp also features a non-conductive ceramic tie bar on the lead frame. the tie bar allows electrical testing of the device, while preserving the lead integrity during shipping and handling, up to the point of lead forming and insertion. packaging 28-lead flat pack (22018131-001) ceramic chip capacitors can be mounted to the package by the user to maximize supply noise decoupling and increase board packing density. these capacitors attach directly to the internal package power and ground planes. this design minimizes resistance and inductance of the bond wire and package. all nc (no connect) pins should be connected to vss to prevent charge build up in the radiation environment. 36-lead fp pinout vdd nwe a13 a8 a9 a11 noe a10 ncs dq7 dq6 dq5 dq4 dq3 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 dq0 dq1 dq2 vss 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 top view 28-lead dip & fp pinout 28-lead dip for 28-lead dip description, see mil-std-1835, type cdip2-t28, config. c, dimensions d-10 vss vdd nwe ce a13 a8 a9 a11 noe a10 ncs dq7 dq6 dq5 dq4 dq3 vdd vss vss vdd a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 dq0 dq1 dq2 nc vdd vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 top view
11 HLX6256 vdd = 3.9v, r 10 k ? , vih = vdd, vil = vss ambient temperature 125 c, f0 100 khz sq wave frequency of f1 = f0/2, f2 = f0/4, f3 = f0/8, etc. vdd = 3.6v min., r 10 k ? ambient temperature 125 c 36-lead flat pack (22018131-001) [1] parts delivered with leads unformed [2] at tie bar [3] lid tied to vss a b c d e e f g h i j l 0.095 0.014 0.008 0.002 0.005 to 0.0075 0.650 0.010 0.630 0.007 0.025 0.002 [2] 0.425 0.005 [2] 0.525 0.005 0.135 0.005 0.030 0.005 0.080 typ. 0.285 0.015 m n o p r s t u v w x y 0.008 0.003 0.050 0.010 0.090 ref 0.015 ref 0.075 ref 0.113 0.010 0.050 ref 0.030 ref 0.080 ref 0.005 ref 0.450 ref 0.400 ref all dimensions are in inches [1] kovar lid [3] ceramic body a j i c m 0.004 n x vdd optional capacitors 1 f vss v s w p u 1 y vdd vss o t r non- conductive tie-bar d b (width) e (pitch) e 1 h g l l t o p v i e w 22018131-001 r f0 f15 f12 f11 f10 f17 f9 f17 f1 f1 f1 f1 f1 vss vdd 32k x 8 sram a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 dq0 dq1 dq2 vss vdd nwe a13 a8 a9 a11 noe a10 ncs dq7 dq6 dq5 dq4 dq3 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 f16 f7 f6 f5 f4 f3 f2 f8 f13 f14 f1 f1 f1 r r r r r r r r r r r r r r r r r r r r r r r r r vss vdd 32k x 8 sram a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 dq0 dq1 dq2 vss vdd nwe a13 a8 a9 a11 noe a10 ncs dq7 dq6 dq5 dq4 dq3 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 vdd r r r r r r r r r r r r r r r r r r r r r r r r r r r dynamic burn-in diagram* static burn-in diagram* *36-lead flat pack burn-in diagram has similar connections and is available on request.
HLX6256 12 helping you control your world ordering information (1) honeywell reserves the right to make changes to any products or technology herein to improve reliability, function or design. h oneywell does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. lx process lx=low power soi h source h=honeywell h total dose hardness r=1x10 5 rad(sio 2 ) f=3x10 5 rad(sio 2 ) h=1x10 6 rad(sio 2 ) n=no level guaranteed s screen level v=qml class v q=qml class q s=level s b=level b e=engineering device (2) n package designation n=28-lead fp r=28-lead dip x=36-lead fp k=known good die - = bare die (no package) part number 6256 900160 2/96 to learn more about honeywell solid state electronics center, visit our web site at http://www.ssec.honeywell.com (1) orders may be faxed to 612-954-2051. please contact our customer logistics department at 612-954-2888 for further informatio n. (2) engineering device description: parameters are tested from -55 to 125 c, 24 hr burn-in, no radiation guaranteed. contact factory with other needs.

▲Up To Search▲

Price & Availability of HLX6256

	To Download HLX6256 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .